The present disclosure relates to a Programmable Logic Controller (PLC) device and a method for controlling the same.
The present disclosure relates to a Programmable Logic Controller (PLC) device and a method for controlling the same. More specifically, the present disclosure relates to a PLC device for outputting a performance result while a sequence program is performed with a plurality of calculation processes, and a method for controlling the same. Unlike a typical PLC sequence program (which accesses a memory in order to output a calculation result), the method accesses an Application Specific Integrated Circuit (ASIC) in order to output a calculation result, so that confirmation may be made on the calculation result while a sequence program is performed.
A PLC is a highly autonomous control device, which replaces a relay control board function such as a relay timer and a counter in a conventionally-used control board with a semiconductor device such as a Large Scale Integration (LSI) chip and a transistor in order to add a mathematical function to a basic sequence control function for a program control, and scans the start and end of a program in a memory to perform a logic operation.
FIGS. 1 and 2 are views illustrating a configuration of a typical PLC device.
As shown in FIGS. 1 and 2, the typical PLC device includes an input circuit 200, a control unit 100, and an output circuit 300.
The input circuit 200 receives an input signal or input data from an external. The input circuit 200 may include resistors R1 and R2 connected in series and parallel, a data input unit 220 for delivering an input signal to the control unit 100, and a first photo coupler 210. The first photo coupler 210 completely insulates the input circuit 200 from the output circuit 230, thereby delivering an input signal but preventing an external disturbance signal from being delivered to the control unit 100.
The output circuit 300 outputs output data, i.e. a calculation result on the input data. The output circuit 300 may include a second photo coupler 310, a resistor R3, a switching device 320, and a data output unit 330.
The control unit 100 performs a calculation operation on the input data and controls other data inputs/outputs. The control unit 100 includes a controller 110 for controlling the data input unit 220 and the data output unit 330 and a memory 120 for storing input/output data.
The data input unit 220 and the data output unit 330 may use an ASIC or a Field Programmable Gate Array (FPGA).
When the ASIC is used, it includes a storage area for temporarily storing data to be processed internally. Additionally, an address for access is assigned to the storage area. When accessing the data input unit 220, the controller 110 has an address for a specific area in the data input unit 220. In the same manner, when accessing the data output unit 330, the controller 110 has an address for a specific area in the data output unit 330.
As shown in FIG. 1, according to a conventional way, when the controller 110 reads input data, the input data are stored in the memory 130 first; a chip selection command CS and a read command RD are delivered to the data input unit 220; and then, the data input unit 220 reads the input data from the memory 120.
Additionally, as shown in FIG. 2, according to a conventional way, when data are outputted to an external, a writing command WR is delivered to the data output unit 330 in order to be recorded on a memory; the address of data to be outputted and a read command RD are delivered to the data output unit 330; and then, the data output unit 330 reads the data to be outputted from the memory and delivers them to an external.
That is, a conventional PLC device has an issue in terms of wasting memory space.
Moreover, in general, a conventional PLC device does not transmit/receive data to/from an input/output port during a program calculation operation. Since all program calculation operations need to be completed before data are outputted and a calculation result is confirmed, input/output data loss occurs.
For example, when data are stored in an output image area of an i-address at least two times during a program calculation operation, the last stored data are outputted to an output port. Accordingly, when an output of the i-address is required to be changed N times during program execution, the program needs to be programmed in order to be performed at least N times.
When j-address input data are changed during an Nth program calculation operation, since a j-address input image area is updated before an N+1th program calculation operation, the changed data may not be used in the Nth program calculation operation.
If the data, which are changed during the Nth program calculation operation, are changed again before the Nth program calculation operation is finished, it is not recognized that the input is changed during program execution.